(1) Field of the Invention
This invention relates to a phase coincidence detector for generating a phase coincidence signal representing whether or not the phases of two signals are coincident, and more particularly to a phase coincidence detector suitable for a phase-locked loop (PLL) using a digital frequency/phase comparator.
(2) Description of the Prior Art
A phase comparator with a function of a frequency discriminator will be herein referred to as a "frequency/phase comparator" and simply the "phase comparator" unless specified otherwise. The phase coincidence signals obtained easily from these phase comparators in accordance with the prior art involve the problem in that they become pulsive signals as will be explained below.
FIG. 2 of the accompanying drawings shows a phase comparator 1 and a phase coincidence detector 2 employed in RCA CMOS Integrated Circuit CD4046A (RCA, Application Note ICAN-6101). The phase comparator 1 consists of nine NOR gates as shown in the drawing, and outputs a delay signal UP (a signal indicating that the phase of a signal V lags behind the phase of a signal R) from a terminal UP in accordance with the phase difference between the digital signal R inputted to a terminal 4 and the digital signal V inputted to a terminal 5 and an advance signal DW (a signal indicating that the phase of the signal V advances with respect to the phase of the signal R) from the terminal DW. The phase coincidence detector 2 outputs the NOR logic output between the delay signal UP and the advance signal DW as a signal LD representing the coincidence state from a terminal 7 (hereinafter referred to as the "coincidence signal").
FIG. 3 shows examples of operating waveforms of the circuit shown in FIG. 2. A time region I represents the case where the phase of the signal V delays with respect to the signal R. The delay signal UP is at the "high" level for a period corresponding to the phase difference of both signals while the advance signal DW becomes a residual pulse having a small pulse, width. A time region II represents the case where the phases of the signals R and V are coincident, and both the signals UP and DW become residual pulses having a small pulse width. A time region III represents the case where the phase of the signal V advances with respect to the signal R. The advance signal becomes the high level for a period corresponding to the phase difference of both signals while the delay signal becomes a residual pulse having a small pulse width.
Incidentally, FIG. 3 shows one period for each of the time regions I, II and III for the sake of simple description, and the waveforms of these regions occur repeatedly in practice. The residual pulses appearing in the signals UP and DW are inevitable because the logic gates constituting the phase comparator have a delay time.
Therefore, the coincidence signal LD as the NOR signal between the signal UP and the signal DW exhibits a waveform wherein a negative pulses 8 having a pulse width corresponding to the phase difference between the signals R and V or negative residual pulses 9 occurs according to phase relations between the signals R and V. Therefore, the prior art involves the problem in that it cannot discriminate whether or not the phases are coincident only from a level at any instantaneous time.
When a phase-locked loop is constituted by use of the phase comparator 1 shown in FIG. 2, the phase of the signals R and V become substantially the same if the loop is in a locked state. However, the coincidence signal LD outputted from the phase coincidence detector 2 becomes a periodic signal consisting of the residual pulse 9 shown in FIG. 3 or a pulse having a somewhat greater pulse width than the width of the residual 9 shown corresponding to the residual phase difference between the signal R and the signal V. On the other hand, when the loop is out of coincidence, the phase relationship between the signals R and V changes at random so that the coincidence signal LD becomes a signal having a random pulse width. The pulsive coincidence signal LD should be integrated by analog circuits or softwares in order that other circuits for example, a logic controller or a microprocessor may monitor whether or not the phase-locked loop is in a locked state. However, there is the problem that the selection range of the charging time constant and the discharging time constant for the integration is small because the coincidence signal LD consists of pulses having a random pulse width.